DS92LV1212AMSA Datasheet, PDF (7/17 Pages) Texas Instruments – DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
t_RCP
Receiver out Clock
Figure 3
RCLK
25
Period
t_RCP = t_TCP
t_CLH
CMOS/TTL Low-to-High
CL = 15 pF
Transition Time
Figure 2
Rout(0-9),
62.5
ns
1.2
4
ns
t_CHL
CMOS/TTL High-to-Low
Transition Time
LOCK, RCLK
1.1
4
ns
t_DD
Deserializer Delay
Figure 4
All Temp./All Freq. 1.75*t_RCP+ 1.25 1.75*t_RCP+3.75 1.75*t_RCP+6.25 ns
Room Temp
3.3V/40MHz
1.75*t_RCP+ 2.25 1.75*t_RCP+3.75 1.75*t_RCP+5.25
t_ROS
ROUT (0-9) Setup Data to Figure 5
RCLK
RCLK
0.4*t_RCP
0.5*t_RCP
ns
t_ROH
ROUT (0-9) Hold Data to
RCLK
−0.4*t_RCP
−0.5*t_RCP
ns
t_RDC
t_HZR
t_LZR
t_ZHR
t_ZLR
t_DSR1
RCLK Duty Cycle
HIGH to TRI-STATE Delay Figure 6
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer PLL Lock Time Figure 7
from PWRDWN (with
Figure 8
SYNCPAT)
(Note 4)
Rout(0-9),
LOCK
16MHz
40MHz
45
50
55
%
4.2+0.5*t_RCP
10+t_RCP
ns
4.5+0.5*t_RCP
10+t_RCP
ns
6+0.5*t_RCP
12+t_RCP
ns
6.0+0.5*t_RCP
12+t_RCP
ns
4
10
µs
1.31
3
µs
t_DSR2
Deserializer PLL Lock time
from SYNCPAT
16MHz
40MHz
1.2
5
µs
0.47
1
µs
t_ZHLK
TRI-STATE to HIGH Delay
(Power-up)
LOCK
4.62
12
ns
t_RNM Deserializer Noise Margin Figure 9
16 MHz
900
1100
ps
(Note 5)
40 MHz
450
730
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH
and VTL which are differential voltages.
Note 4: For the purpose of specifying Deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the Deserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time required
for the Deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before initiating
either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled Deserializer when the input (RI+ and RI-) conditions change from not
receiving data to receiving synchronization patterns (SYNCPATs).
Note 5: tRNM is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur.
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