DS92LV1212AMSA Datasheet, PDF (14/17 Pages) Texas Instruments – DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

Pin Diagram
DS92LV1212AMSA - Deserializer
Deserializer Pin Description
Pin Name
ROUT
RCLK_R/F
I/O
No.
O
15–19,
24–28
I
2
RI+
RI−
PWRDN
LOCK
I
5
I
6
I
7
O
10
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
O
9
I
8
I
21, 23
I
14, 20, 22
I
4, 11
I
1, 12, 13
I
3
DS101387-19
Description
Data Output. ±9 mA CMOS level outputs.
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL.
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
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