DS92LV1212AMSA Datasheet, PDF (15/17 Pages) Texas Instruments – DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

Truth Table
PWRDN
H
H
L
H
INPUTS
REN
H
H
X
L
ROUT [0:9]
Z
Active
Z
Z
OUTPUTS
LOCK
H
L
Z
Active
RCLK
Z
Active
Z
Z
1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
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