DS90CR218A_14 Datasheet, PDF (7/17 Pages) Texas Instruments – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

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DS90CR218A
SNLS054D – NOVEMBER 1999 – REVISED APRIL 2013
Figure 11. Receiver LVDS Input Strobe Position
Ideal Strobe Position
RxIN+ or RxIN-
RxIN+ or RxIN-
RSKM
Tppos Ideal
C
min
max
Rsposn
RSKM
Tppos Ideal
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos Ideal — Calculated Transmitter output pulse position
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (Cycle-to-cycle)⁽¹⁾ + ISI (Inter-symbol interference) + TPPOS
variance (Tx dependent)⁽²⁾
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than 250 ps at 85MHz
(2) ISI is dependent on interconnect length; may be zero
Figure 12. Receiver LVDS Input Skew Margin
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