DS90CR218A_14 Datasheet, PDF (4/17 Pages) Texas Instruments – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz

DS90CR218A
SNLS054D – NOVEMBER 1999 – REVISED APRIL 2013
Electrical Characteristics⁽¹⁾ (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
I_CCRZ
Receiver Supply Current⁽²⁾ Power Down
Conditions
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
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Min Typ Max Units
140 400 μA
Receiver Switching Characteristics⁽¹⁾
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time Figure 5
CHLT
CMOS/TTL High-to-Low Transition Time Figure 5
RSPos0
Receiver Input Strobe Position for Bit 0 Figure 11
f = 85 MHz
RSPos1
Receiver Input Strobe Position for Bit 1
RSPos2
Receiver Input Strobe Position for Bit 2
RSPos3
Receiver Input Strobe Position for Bit 3
RSPos4
Receiver Input Strobe Position for Bit 4
RSPos5
Receiver Input Strobe Position for Bit 5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin⁽²⁾ Figure 12
f = 85 MHz
f = 12MHz
RCOP
RxCLK OUT Period Figure 6
RCOH
RxCLK OUT High Time Figure 6
f = 85 MHz
RCOL
RxCLK OUT Low Time Figure 6
RSRC
RxOUT Setup to RxCLK OUT Figure 6
RHRC
RCCD
RPLLS
RxOUT Hold to RxCLK OUT Figure 6
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 3.3V⁽³⁾ Figure 7
Receiver Phase Lock Loop Set Figure 8
RPDD
Receiver Powerdown Delay Figure 10
Min
0.49
2.17
3.85
5.53
7.21
8.89
10.57
11.76
4
3.5
3.5
3.5
5.5
Typ
2.0
1.8
0.84
2.52
4.20
5.88
7.56
9.24
10.92
0.49
2.01
T
5
5
7
Max
3.5
3.5
1.19
2.87
4.55
6.23
7.91
9.59
11.27
83.33
6.5
6
9.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
(1) Typical values are given for V_CC = 3.3V and T_A = +25°C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the receiver
input setup and hold time (internal data sampling window). This margin do not take into account the Transmitter Pulse Position (TPPOS)
variance and is measured using the ideal TPPOS. This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and source clock jitter less than 250 ps.
(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the 217/287 transmitter and 218A/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
Figure 4. “Worst Case” Test Pattern
4
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