DS90CP02 Datasheet, PDF (7/14 Pages) Texas Instruments – DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch

Symbol
Parameter
Conditions
Min
SUPPLY CURRENT (Static)
I_CC0
Supply Current
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
I_CC1
Supply Current - one channel
Single channel crossover switch or single
powered down
channel repeater modes (1 channel
active, one channel in power down mode)
I_CC2
Supply Current - one input powered Splitter mode (One input powered down,
down
both outputs active)
I_CCZ
TRI-STATE Supply Current
Both input/output Channels in Power
Down Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figures 3, 4)
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at 200
70
Time
Mb/s, measure between 20% and 80% of
t_HLT
Differential High to Low Transition ^VOD^.
Time
50
t_PLHD
t_PHLD
Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200
0.5
Delay
Mb/s, measure at 50% V_OD between
Differential High to Low Propagation ^{input to output.}
Delay
0.5
t_SKD1
Pulse Skew
|t_PLHD–t_PHLD|
t_SKCC
Output Channel to Channel Skew Difference in propagation delay (t_PLHD or
t_PHLD) among all output channels in
0
Splitter mode (any one input to all
outputs).
t_JIT
Jitter
(Note 5)
RJ - Clock Pattern
750 MHz (Note 6)
DJ - K28.5 Pattern
1.5 Gbps (Note 7)
TJ - PRBS 2²³-1 Pattern
1.5 Gbps (Note 8)
t_ON
LVDS Output Enable Time
Time from ENx to OUT± change from
TRI-STATE to active.
50
t_OFF
LVDS Output Disable Time
Time from ENx to OUT± change from
active to TRI-STATE.
t_SW
LVDS Switching Time
SELx to OUT±
Time from configuration select (SELx) to
new switch configuration effective for
OUT±.
Typ
(Note 2)
42
22
30
1.4
150
135
2.4
2.4
55
130
1.4
42
93
110
5
110
Max
60
30
40
2.5
215
180
3.5
3.5
120
315
2.5
75
126
150
12
150
Units
mA
mA
mA
mA
ps
ps
ns
ns
ps
ps
psrms
psp-p
psp-p
ns
ns
ns
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters are measured at V_DD = 3.3V, T_A = 25°C. They are for reference purposes, and are not production-tested.
Note 3: Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
Note 4: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 5: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 6: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50% duty cycle at
750MHz, t_r = t_f = 50ps (20% to 80%).
Note 7: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V_ID = 500mV, K28.5 pattern at 1.5 Gbps,
t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 8: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage
= V_ID = 500mV, 2²³-1 PRBS pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%).
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