DS90CP02 Datasheet, PDF (3/14 Pages) Texas Instruments – DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch

Pin Descriptions
Pin
Name
Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN0+
IN0−
9
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
10
compatible.
IN1+
IN1−
12
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
13
compatible.
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+
27
OUT0−
26
O, LVDS
Inverting and non-inverting differential outputs. OUT0± can be connected to any one pair
IN0±, or IN1±. LVDS compatible .
OUT1+
24
OUT1−
23
O, LVDS
Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair
IN0±, or IN1±. LVDS compatible .
DIGITAL CONTROL INTERFACE
SEL0,
6
I, LVTTL
Select Control Inputs
SEL1
5
EN0, EN1
7
15
I, LVTTL
Output Enable Inputs
N/C
8, 20, 28
Not Connected
POWER
V_DD
11, 14, 16,
I, Power
V_DD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected
18, 19, 22,
from V_DD to GND plane.
25
GND
DAP, 1, 2,
3, 4, 17, 21
I, Power
Ground reference to LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the device. The
DAP is the exposed metal contact at the bottom of the LLP-28 package. It should be
connected to the ground plane with at least 4 vias for optimal AC and thermal
performance.
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