DS90C032_16 Datasheet, PDF (7/18 Pages) Texas Instruments – Quad CMOS Differential Line Receiver

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TYPICAL APPLICATION
DS90C032
SNLS094D – JUNE 1998 – REVISED APRIL 2013
Figure 6. Point-to-Point Application
APPLICATIONS INFORMATION
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of mid-stream connectors, cable stubs, and other impedance discontinuities as well as ground
shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C032 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-
mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The
driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins
should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
Receiver Fail-Safe
The LVDS receiver is a high-gain high-speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source or sink a small amount of current, providing fail-
safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs.
1. Open Input Pins. TheDS90C032 is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high-value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH stable output state for open inputs.
2. Terminated Input. TheDS90C032 requires external failsafe biasing for terminated input failsafe.
Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the
driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in power-
off condition. The use of external biasing resistors provide a small bias to set the differential input voltage
while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed
from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna
that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and
recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the
receiver may respond. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common
to both lines and rejected by the receivers.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (1.2V ±1V). It is only supported with inputs shorted
and no external common-mode voltage applied.
4. Operation in environment with greater than 10mV differential noise.
TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal
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