BUF12840_15 Datasheet, PDF (7/31 Pages) Texas Instruments – Programmable Gamma-Voltage Generator

BUF12840
www.ti.com
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
APPLICATION INFORMATION
GENERAL
The BUF12840 programmable voltage reference
allows fast and easy adjustment of 12 programmable
gamma reference outputs, each with 10-bit resolution.
The BUF12840 is programmed through a high-speed,
two-wire interface. The final gamma values can be
automatically loaded from an external EEPROM. The
BUF12840 has two separate memory banks, allowing
simultaneous storage of two different gamma curves
to facilitate dynamic switching between gamma
curves.
The BUF12840 can be powered using an analog
supply voltage from 9V to 20V, and a digital supply
from 2V to 5.5V. The digital supply must be applied
before the analog supply to avoid excessive current
and power consumption, or possibly even damage to
the device if left connected only to the analog supply
for extended periods of time. See Figure 10 for a
typical configuration of the BUF12840. Note that the
analog power, V_S, does not need to be on during any
interface communication.
TWO-WIRE BUS OVERVIEW
The BUF12840 communicates over an
industry-standard, two-wire interface to receive data
in slave mode. This model uses a two-wire,
open-drain interface that supports multiple devices on
a single bus. Bus lines are driven to a logic low level
only. The device that initiates the communication is
called a master, and the devices controlled by the
master are slaves. The master generates the serial
clock on the clock signal line (SCL), controls the bus
access, and generates the START and STOP
conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line (SDA)
from a high to a low logic level while SCL is high. All
slaves on the bus shift in the slave address byte on
the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
high. Any change in SDA while SCL is high is
interpreted as a START or STOP condition.
Once all data have been transferred, the master
generates a STOP condition, indicated by pulling
SDA from low to high while SCL is high. The
BUF12840 acts as a slave device after 10ms; before
that, it is the master and drives SCL and SDA.
ADDRESSING THE BUF12840
The address of the BUF12840 is 111010x, where x is
the state of the A0 pin. When the A0 pin is low, the
device acknowledges on address 74h (1110100). If
the A0 pin is high, the device acknowledges on
address 75h (1110101). Table 1 shows the A0 pin
settings and the BUF12840 address options.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
Table 1. Quick Reference of BUF12840 Addresses
BUF12840 ADDRESS
A0 pin is low
(device acknowledges on address 74h)
A0 pin is high
(device acknowledges on address 75h)
ADDRESS
1110100
1110101
COMMAND
General-Call Reset
High-Speed Mode
Table 2. Quick Reference of Command Codes
CODE
Address byte of 00h followed by a data byte of 06h.
00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
Copyright © 2010–2011, Texas Instruments Incorporated
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