BUF12840_15 Datasheet, PDF (10/31 Pages) Texas Instruments – Programmable Gamma-Voltage Generator

BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
EEPROM ADDRESS SELECT PINS
EA0 and EA1 are used to select the proper EEPROM
size. Table 4 shows the start and stop address to
load each of the DAC registers. The state of the
select pins must be set before the auto read function
is activated.
Enable Pin
The status of EN at power-on reset (POR)
determines the modes of operation of the BUF12840,
as described in Table 3. If EN = 1, the BUF12840
acts as a master; after the data download finishes,
the BUF12840 enters slave mode. If EN = 0, the
BUF12840 skips the master mode and enters slave
mode directly. Once in slave mode after POR,
changing the status of EN has no effect on the
BUF12840 unless the user issues a GCR
(general-call reset) or RA (read again) command.
Table 3. EN Modes of Operation
ENABLE EN
Low
High
LOGIC LEVEL
0
1
EEPROM AUTO
READ
Disabled
Enabled
After a POR condition is detected by the BUF12840,
a 10ms window occurs. As long as EN goes high in
this window, the BUF12840 downloads data from the
EEPROM. It is recommended that this pin be tied to
DVDD if the application allows. However, if only slave
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mode operation is needed, EN should be tied to
DVSS; it is recommended that after POR occurs wait
at least 15ms before addressing the BUF12840.
Figure 12 shows how EN affects the operation of the
BUF12840 in a typical application.
The BUF12840 tries to read up to 10 times spaced
1ms apart during POR, which can occur if the
EEPROM is not ready or if the two-wire bus is kept
busy by another device. By the end of the tenth
attempt, if the download cannot be started, the
BUF12840 goes into slave mode. This action ensures
that the BUF12840 enters slave mode within 25ms
from the POR condition, regardless if the download is
successful or not.
POR
Initialize DAC Output
Load DAC with All 0s
Set
No
EN = 1
Yes
EEPROM
Download
The BUF12840
Enters Slave Mode
Figure 12. Effect of EN in a Typical Set Up
Table 4. EEPROM Configuration
EA0
EA1
0
0
0
1
1
0
1
1
REGISTER BANK0
START WORD
ADDRESS
END WORD
ADDRESS
0
23
361
384
0
23
361
384
REGISTER BANK1
START WORD
ADDRESS
END WORD
ADDRESS
24
47
405
428
24
47
405
428
ACCEPTABLE
EEPROM ^{(1) (2)}
1k, 2k, 4k, 8k, 16k
2k, 4k, 8k, 16k
32k, 64k, 128k, 256k
and larger
32k, 64k, 128k, 256k
and larger
(1) Any applicable EEPROM chip select pins (A2, A1, A0) must be hardwired to GND.
(2) When EA0 = 0 and EA1 = 1, it is required that the types of EEPROM that supports Page/Block address definition with chip select pins
(for example, A0 is part of the Word Address).
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