AMC1305L25-Q1 Datasheet, PDF (7/38 Pages) Texas Instruments – High-Precision, Reinforced Isolated Delta-Sigma Modulators

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AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
SBAS797 – FEBRUARY 2017
7.9 Electrical Characteristics: AMC1305M05-Q1
All minimum and maximum specifications at T_A = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =
–50 mV to 50 mV, AINN = 0 V, and sinc³ filter with OSR = 256, unless otherwise noted. Typical values are at T_A = 25°C,
CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUTS
V_Clipping
Maximum differential voltage input range
(AINP-AINN)
±62.5
mV
FSR
Specified linear full-scale range
(AINP-AINN)
–50
50
mV
V_CM
C_ID
I_IB
R_ID
I_OS
CMTI
Operating common-mode input range
Differential input capacitance
Input current
Differential input resistance
Input offset current
Common-mode transient immunity
Inputs shorted to AGND
–0.032
–97
15
AVDD – 2
2
–72
-57
5
±5
V
pF
μA
kΩ
nA
kV/μs
CMRR
BW
Common-mode rejection ratio
Input bandwidth
f_IN = 0 Hz,
V_{CM min} ≤ V_IN ≤ V_{CM max}
f_IN from 0.1 Hz to 50 kHz,
V_{CM min} ≤ V_IN ≤ V_{CM max}
–104
dB
–75
800
kHz
DC ACCURACY
DNL
INL
Differential nonlinearity
Integral nonlinearity⁽¹⁾
Resolution: 16 bits
Resolution: 16 bits
–0.99
0.99
LSB
–5
±1.5
5
LSB
E_O
TCE_O
E_G
TCE_G
PSRR
Offset error
Offset error thermal drift⁽²⁾
Gain error
Gain error thermal drift⁽³⁾
Power-supply rejection ratio
AC ACCURACY
Initial, at 25°C
Initial, at 25°C
V_AVDD from 4.5 to 5.5V, at dc
–50
–1.3
–0.3%
–40
±2.5
–0.02%
±20
105
50
1.3
0.3%
40
µV
μV/°C
ppm/°C
dB
SNR
Signal-to-noise ratio
SINAD
Signal-to-noise + distortion
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
DIGITAL INPUTS/OUTPUTS
f_IN = 1 kHz
f_IN = 1 kHz
f_IN = 1 kHz
f_IN = 1 kHz
76
81
dB
76
81
dB
–90
–83
dB
83
92
dB
External Clock
f_CLKIN
Input clock frequency
Duty_CLKIN
Duty cycle
CMOS Logic Family, CMOS with Schmitt-Trigger
5 MHz ≤ f_CLKIN ≤ 20.1 MHz
5
40%
20
50%
20.1
60%
MHz
I_IN
C_IN
V_IH
V_IL
C_LOAD
V_OH
V_OL
Input current
Input capacitance
High-level input voltage
Low-level input voltage
Output load capacitance
High-level output voltage
Low-level output voltage
DGND ≤ V_IN ≤ DVDD
f_CLKIN = 20 MHz
I_OH = –20 µA
I_OH = –4 mA
I_OL = 20 µA
I_OL = 4 mA
–1
0.7 × DVDD
–0.3
DVDD – 0.1
DVDD – 0.4
1
μA
5
pF
DVDD + 0.3
V
0.3 × DVDD
V
30
pF
V
0.1
V
0.4
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(2)
Offset error drift is calculated using the box method as described by the following equation: ^TCEO
value_MAX value_MIN
TempRange
(3)
TCE _G ( ppm)
Gain error drift is calculated using the box method as described by the following equation:
¨¨©§
value _MAX value _MIN
value u TempRange
¸¸¹· ^{u10 6}
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