AMC1305L25-Q1 Datasheet, PDF (21/38 Pages) Texas Instruments – High-Precision, Reinforced Isolated Delta-Sigma Modulators

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8.3 Feature Description
AMC1305L25-Q1, AMC1305M05-Q1, AMC1305M25-Q1
SBAS797 – FEBRUARY 2017
8.3.1 Analog Input
The AMC1305-Q1 incorporates front-end circuitry that contains a differential amplifier and sampling stage,
followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of
4 for devices with a specified input voltage range of ±250 mV (for the AMC1305x25-Q1), or to a factor of 20 for
devices with a ±50-mV input voltage range (for the AMC1305M05-Q1), resulting in a differential input impedance
of 5 kΩ (for the AMC1305M05-Q1) or 25 kΩ (for the AMC1305x25-Q1).
Consider the input impedance of the AMC1305-Q1 in designs with high-impedance signal sources that can
cause degradation of gain and offset specifications. The importance of this effect, however, depends on the
desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at
the output of the differential amplifier causes an offset that depends on the actual amplitude of the input signal.
See the Isolated Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range of AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) protection diodes turn on. In addition, the linearity and noise performance of the
device are ensured only when the differential analog input voltage remains within the specified linear full-scale
range (FSR), that is ±250 mV (for the AMC1305x25-Q1) or ±50 mV (for the AMC1305M05-Q1), and within the
specified input common-mode range.
8.3.2 Modulator
The modulator implemented in the AMC1305-Q1 is a second-order, switched-capacitor, feed-forward ΔΣ
modulator, such as the one conceptualized in Figure 48. The analog input voltage V_IN and the output V₅ of the 1-
bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V₁ at the input of the first
integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in
output voltage V₃ that is differentiated with the input signal V_IN and the output of the first integrator V₂. Depending
on the polarity of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC
responds on the next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in
the opposite direction while forcing the value of the integrator output to track the average value of the input.
f_CLKIN
V₁
V₂
V₃
V₄
V_IN
Integrator 1
Integrator 2
CMP
0V
V₅
DAC
Figure 48. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies; see Figure 49. Therefore, use a low-pass digital
filter at the output of the device to increase overall performance. This filter is also used to convert from the 1-bit
data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller
family TMS320F2837x offers a suitable programmable, hardwired filter structure termed a sigma-delta filter
module (SDFM) optimized for usage with the AMC1305-Q1 family. Alternatively, a field-programmable gate array
(FPGA) can be used to implement the digital filter.
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