TNETX15AEPGE Datasheet, PDF (69/79 Pages) Texas Instruments – ADDRESS-LOOKUP DEVICE

TNETX15AE
ADDRESS-LOOKUP DEVICE
SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997
timing requirements (see Note 7 and Figure 21)
DIO read cycle
NO.
MIN MAX UNIT
1 tw(ESCSL) Pulse duration, ESCS low
40
ns
2 tsu(SRNW) Setup time, SRNW high before ESCS↓
3
ns
3 tsu(SAD)
Setup time, SAD1–SAD0 valid before ESCS↓
3
ns
NOTE 7: The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be
run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed.
The TNETX15AE withholds the SRDY acknowledge signal on registers until it has gathered the necessary data.
operating characteristics over recommended operating conditions (see Note 7 and Figure 22)
DIO read cycle
NO.
PARAMETER
MIN MAX UNIT
4† tw(SRDYH) Pulse duration, SRDY high
25 ns
5 td(SRNW) Delay time, from SRDY↓ to SRNW↓
0
ns
6 td(SAD)
Delay time, from SRDY↓ to SAD1–SAD0 invalid
0
ns
7 td(SDATA)1 Delay time, from SRDY↓ to SDATA7–SDATA0 valid
5
ns
8 td(ESCS)
Delay time, from SRDY↓ to ESCS↑
0
ns
9 td(SDATA)2 Delay time, from ESCS↑ to SDATA7–SDATA0 high-impedance Z
17 ns
10† td(SRDY)1 Delay time, from ESCS↓ to SRDY↓
40
‡ ns
11† td(SRDY)2 Delay time, from ESCS↑ to SRDY↑
0
25 ns
† _{These parameters are specified by design, but not tested.}
‡ _{Max = min + N (internal cycles), where N equals the number of internal cycles required to arbitrate internally to obtain the value being requested.}
N is equal to a minimum of 1, and can be large during RAM INIT and FINDNEXT operation, since DIO operations will not complete during these
operations ( no SRDY true), and both of these operations can read every SRAM location to finish.
NOTE 7: The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be
run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed.
The TNETX15AE withholds the SRDY acknowledge signal on DIO accesses until it has gathered the necessary data.
ESCS
(Input)
SRNW
(Input)
ÎÎÎÎÎÎ _{SAD1–SAD0}
ÎÎÎÎÎÎ ^(Input)
SDATA7–SDATA0
(Output)
SRDY
(Output) ^Z
9
1
11
2
5
3
6
Host Address
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
7
Z
Z
Data
10
8
4
Z
Figure 22. DIO Read Cycle
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