TNETX15AEPGE Datasheet, PDF (36/79 Pages) Texas Instruments – ADDRESS-LOOKUP DEVICE

TNETX15AE
ADDRESS-LOOKUP DEVICE
SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997
PRINCIPLES OF OPERATION
TNETX15AE DRAM and EAM interface (continued)
The TNETX15AE must determine that the data being written to memory is the first buffer of a data frame and
not an IOB index buffer. The buffer contains packet data if the IOB bit is 0. The channel/source port code is
latched from bits DD27–DD24 during the forward pointer (FPTR) transfer when
TNETX3150/TNETX3150A/TNETX3100 is writing packet data to DRAM.
The TNETX15AE must determine the start of frame by looking at the flag in cycle 1. The flag is given in the
DD35–DD32 terminals. The SOF is shown in the following table in cycle 1 at bit (35–34) = 01b.
CYCLE
35
0
IOB
34
33
32
Parity†
1
0
1
Reserved
2
Channel code†
3
0
0
Reserved
•
•
Flags†
•
N–1 EOB
Valid bytes†
N
EOF
Frame status†
† _{These bits are ignored by the TNETX15AE.}
BIT
31
28 27
24 23
16 15
0
Tag†
Channel code
Forward pointer†
Most-significant 32 bits of DA
Most-significant 16 bits SA
Least-significant 16 bits DA
Least-significant 32 bits of SA
Data†
Data†
CRC
The TNETX15AE destination lookup cycle begins when it latches the partial destination address to begin the
table lookup in cycle 1, and ends when it outputs an EAM code within the allocated 440 ns after the SOF
condition is met. It must pick up the 16 bits at the destination in cycle 2 to complete the decode.
The channel-code field in the body of the frame is exactly the same as that in the forward pointer. The
TNETX15AE uses the channel code from the forward pointer.
decoding the destination address (DA) and source address (SA) from the DRAM bus
The TNETX3150/TNETX3150A/TNETX3100 writes data to the DRAM buffers in a specific format (refer to the
TNETX3150/TNETX3150A/TNETX3100 data sheet for additional information on this format). The TNETX15AE
recognizes this format to determine the correct destination and source addresses. The format for the DA and
the SA is shown in the following:
BIT
CYCLE
31
25 24
16 15
87
0
1
DA23–DA16 DA31–DA24
DA39–32
DA47–DA40
2
SA39–SA32 SA47–SA40 DA7–DA0
DA15–DA8
3
SA7–SA0
SA15–SA8 SA23–SA16 SA31–SA24
The TNETX15AE will latch and save the source address, cycles 2 and 3, if it is not already saving one. A
source-address lookup will take place when there is no activity (TNETX3150/TNETX3150A/TNETX3100 to
DRAM), when the transfer to memory is not the first 64 bytes of a packet, or when the transfer is from memory
to an output FIFO.
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