TM4C1237H6PM Datasheet, PDF (689/1278 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237H6PM Microcontroller
Figure 11-2. Reading the RTC Value
Read Timer B = B₁
Read Timer A = A₁
Read Predivider
Read Timer A = A₂
Does
no
A₁=A₂?
yes
Read Timer B = B₂
Does
no
B₁=B₂?
yes
Done
In addition to generating interrupts, the RTC can generate a μDMA trigger. The μDMA trigger is
enabled by configuring and enabling the appropriate μDMA channel. See “Channel
Configuration” on page 566.
11.3.2.3
Input Edge-Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Count mode, the timer is configured as a 24-bit or 48-bit up- or up- or down-counter including
the optional prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR)
register and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing
three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode,
the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts
is determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count
mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference
between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and
GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode,
the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note
that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater
June 12, 2014
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