TM4C1237H6PM Datasheet, PDF (329/1278 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237H6PM Microcontroller
Register 58: General-Purpose Input/Output Run Mode Clock Gating Control
(RCGCGPIO), offset 0x608
The RCGCGPIO register provides software the capability to enable and disable GPIO modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the GPIO modules. To support
legacy software, the RCGC2 register is available. A write to the RCGC2 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC2 register can be read back correctly with a read of the RCGC2 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as GPIO A), the write
causes proper operation, but the value of that bit is not reflected in the RCGC2 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO)
Base 0x400F.E000
Offset 0x608
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
R5
R4
R3
R2
R1
R0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
R5
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Port F Run Mode Clock Gating Control
Value Description
0 GPIO Port F is disabled.
1 Enable and provide a clock to GPIO Port F in Run mode.
4
R4
RW
0
GPIO Port E Run Mode Clock Gating Control
Value Description
0 GPIO Port E is disabled.
1 Enable and provide a clock to GPIO Port E in Run mode.
June 12, 2014
329
Texas Instruments-Production Data