TM4C1237H6PM Datasheet, PDF (1001/1278 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237H6PM Microcontroller
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CLKIM
IM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
CLKIM
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Timeout Interrupt Mask
Value Description
0 The CLKRIS interrupt is suppressed and not sent to the interrupt
controller.
1 The clock timeout interrupt is sent to the interrupt controller
when the CLKRIS bit in the I2CMRIS register is set.
0
IM
RW
0
Master Interrupt Mask
Value Description
0 The RIS interrupt is suppressed and not sent to the interrupt
controller.
1 The master interrupt is sent to the interrupt controller when the
RIS bit in the I2CMRIS register is set.
June 12, 2014
Texas Instruments-Production Data
1001