CC2400_08 Datasheet, PDF (67/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
MANOR (0x13) - Manual signal OR override register³
Bit
15
Field Name
VGA_RESET_N
14
LOCK_STATUS
13
BALUN_CTRL
12
RXTX
11
PRE_PD
10
PA_N_PD
9
PA_P_PD
8
DAC_LPF_PD
7
BIAS_PD
6
XOSC16M_PD
5
CHP_PD
4
FS_PD
3
ADC_PD
2
VGA_PD
1
RXBPF_PD
0
LNAMIX_PD
Reset R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Overrides VGA_RESET_N used to reset the peak detectors in
the VGA in the RX chain.
Overrides the LOCK_STATUS top-level signal that indicates
whether VCO lock is achieved or not.
Overrides the BALUN_CTRL signal that controls whether the PA
should receive its required external biasing (1) or not (0) by
controlling the RX/TX output switch.
Overrides the RXTX signal that controls whether the LO buffers
(0) or PA buffers (1) should be used.
Power down of prescaler.
Power down of PA (negative path).
Power down of PA (positive path). When PA_N_PD=1 and
PA_P_PD=1 the up-conversion mixers are in power down.
Power down of TX DACs.
Power down control of global bias generator + XOSC clock
buffer.
Power down control of 16 MHz XOSC core.
Power down control of charge pump.
Power down control of VCO, I/Q generator, LO buffers.
Power down control of the ADCs.
Power down control of the VGA.
Power down control of complex band-pass receive filter.
Power down control of LNA, down-conversion mixers and front-
end bias.
MDMTST0 (0x14) - Modem Test Register 0
Bit
15:14
13
Field Name
-
TX_PRNG
Reset R/W
0
W0
0
R/W
12
TX_1MHZ_OFFSET_N
0
R/W
11
INVERT_DATA
0
R/W
10
AFC_ADJUST_ON_PACKET 0
R/W
Description
Reserved, write as 0.
When set, the transmitted data is taken from a 10-bit PRNG
instead of from the DIO pin in un-buffered mode or from the
FIFO in buffered mode.
Determines TX IF frequency:
0: 1 MHz (Not used)
1: 0 MHz (During initialization this bit must be set to a logical ’1’.)
When this bit is set the data are inverted (internally) before
transmission, and inverted after reception.
When this bit is set to '1', modem parameters are adjusted for
slow tracking of the received signal as opposed to quick
acquisition when a packet is received in RX.
• ³ See footnote for MANAND register (address 0x0D) for description of the use of this register.
SWRS042A
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