CC2400_08 Datasheet, PDF (41/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
31 Demodulator, Bit Synchronizer and Data Decision
The block diagram for the demodulator,
data slicer and bit synchronizer is shown
in Figure 20. The built-in bit synchronizer
extracts the data rate and performs data
decision. The data decision is done using
over-sampling and digital filtering of the
incoming signal. This improves the
reliability of the data transmission and
provides a synchronous clock in the un-
buffered mode. Using the buffered mode
simplifies the data interface further, as
data can be written and read byte-for-byte
in bursts from the FIFO.
The suggested preamble is a 32 bit
‘(0)10101…’ bit pattern, the same as used
by the packet handling support, see page
29. This is necessary for the bit
synchronizer to synchronize with the
coding correctly.
The data slicer performs the bit decision.
Ideally the two received FSK frequencies
are placed symmetrically around the IF
frequency. However, if there is some
frequency error between the transmitter
and the receiver, the bit decision level
should be adjusted accordingly. In CC2400
this is done automatically by measuring
the two frequencies and by using the
average value as the decision level.
The digital data slicer in CC2400 uses an
average value of the minimum and
maximum frequency deviation detected as
the
comparison
level.
The
MDMTST0.AFC_DELTA register is used to
set the expected deviation of the incoming
signal. Once a shift in the received
frequency larger than half the expected
separation is detected, a bit transition is
recorded and the average value to be
used by the data slicer is calculated.
The actual number of samples used to find
the averaging value can be programmed
and set higher for better data decision
accuracy. This is controlled by the
AFC_SETTLING[1:0] bits. If RX data is
present in the channel when the RX chain
is turned on, then the data slicing estimate
will usually give correct results after 4 bits.
The data slicing accuracy will increase
after this, depending on the
AFC_SETTLING[1:0] bits. If the start of
a transmission occurs after the RX chain
is turned on, the minimum number of bit
transitions (or preamble bits) before
correct data slicing will depend on the
AFC_SETTLING[1:0] bits, as shown in
Table 17. The recommended setting is
11b, requiring 16 data bits of preamble to
fill the averaging filter completely.
The internally calculated average FSK
frequency value gives a measure for the
frequency offset of the receiver compared
to the transmitter. The frequency offset
can
be
read
from
RSSI.RX_FREQ_OFFSET[7:0]. This
information can also be used for an
automatic frequency control, as described
at page 43.
Average
filter
Digital IF
filtering
Frequency
detector
Decimator
Data
filter
Data slicer
comparator
Bit
synchronizer
and data
decoder
Figure 20. Demodulator block diagram
SWRS042A
Page 41 of 83