CC2400_08 Datasheet, PDF (25/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
21 Microcontroller Interface and Pin Configuration
Used in a typical system, CC2400 will
interface to a microcontroller. This
microcontroller must be able to:
• Program CC2400 into different modes
and read back status information via
the 4-wire SPI-bus configuration
interface (SI, SO, SCLK and CSn). In
buffered mode the data signal is also
transmitted through the SPI-bus
• Interface to the bi-directional
synchronous data signal interface (DIO
and DCLK) if un-buffered data
transmission is to be used
• Optionally interface to the general
control and status pins (RX, TX, FIFO,
PKT, GIO1 and GIO6) if the hardware
supported packet handling functions
are to be used
• Optionally the microcontroller can
monitor the general I/O pins (GIO1,
GIO6) for frequency lock status, carrier
sense status, or other status
information
• Optionally, the microcontroller can read
back digital RSSI value and other
status information via the 4-wire SPI
interface
21.1 Configuration interface
The microcontroller interface is shown in
Figure 8. The microcontroller uses a
minimum of 4 I/O pins for the SPI
configuration interface (SI, SO, SCLK and
CSn). All other pins are optional. SO
should be connected to an input at the
microcontroller. SI, SCLK and CSn must
be microcontroller outputs.
The microcontroller pins connected to SI,
SO and SCLK can be shared with other
SPI-interface devices. SO is a high
impedance output as long as CSn is not
activated (active low).
CSn should have an external pull-up
resistor or be set to a high level during
power down mode in order to prevent the
input from floating. SI and SCLK should be
set to a defined level to prevent the input
from floating.
21.2 Signal interface in un-buffered
mode
A bi-directional pin (DIO) is used for data
to be transmitted and received. DCLK
providing the data timing should be
connected to a microcontroller input.
The data is clocked in/out at the positive
edge of DCLK.
21.3 General control and status pins
Optionally, in buffered mode, the FIFO pin
can be used to interrupt the
microcontroller at full/empty FIFO. This pin
should then be connected to a
microcontroller interrupt pin.
Optionally, using the packet handling
support, the PKT pin can be used in
buffered mode to interrupt the
microcontroller when a sync word is
detected (RX mode) and packet is
transmitted (TX mode). This pin should
then be connected to a microcontroller
interrupt pin.
The polarity of FIFO and PKT can be
controlled by the INT register (address
0x23).
Optionally, the RX and TX pins can be
used to change the operating mode of
CC2400 as an alternative to using the SPI
interface strobe commands. These pins
should then be connected to
microcontroller output pins. If the RX and
TX pins are not used, they should be
grounded in order to prevent accidental
change of mode.
Optionally, the GIO1 and GIO6 can be
used to monitor several status signals as
selected by the IOCFG register. The GIO6
pin should be connected to a
microcontroller input pin. See Table 18 for
available signals.
Table 15 gives a summary of the possible
pin configurations in the different operation
modes.
SWRS042A
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