TM4C123GH6PGET Datasheet, PDF (668/1456 Pages) Texas Instruments – Tiva TM4C123GH6PGE Microcontroller

General-Purpose Input/Outputs (GPIOs)
further interrupts. For a level-sensitive interrupt, the external source must hold the level constant
for the interrupt to be recognized by the controller.
Three registers define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 678)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 679)
■ GPIO Interrupt Event (GPIOIEV) register (see page 680)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 681).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 682 and page 684). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
interrupt controller.
For a GPIO level-detect interrupt, the interrupt signal generating the interrupt must be held until
serviced. Once the input signal deasserts from the interrupt generating logical sense, the
corresponding RIS bit in the GPIORIS register clears. For a GPIO edge-detect interrupt, the RIS
bit in the GPIORIS register is cleared by writing a ‘1’ to the corresponding bit in the GPIO Interrupt
Clear (GPIOICR) register (see page 686). The corresponding GPIOMIS bit reflects the masked value
of the RIS bit.
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
10.2.2.1
Interrupts Per Pin
Each pin of GPIO Port P can trigger an interrupt. Each pin has a dedicated interrupt vector and can
be handled by a separate interrupt handler. The PP0 and PQ0 interrupts serve as a master interrupt
and provide a legacy aggregated interrupt version. For interrupt assignments, see Table
2-9 on page 103.
10.2.2.2
ADC Trigger Source
Any GPIO pin can be configured to be an external trigger for the ADC using the GPIO ADC Control
(GPIOADCCTL) register. If any GPIO is configured as a non-masked interrupt pin (the appropriate
bit of GPIOIM is set), and an interrupt for that port is generated, a trigger signal is sent to the ADC.
If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger,
an ADC conversion is initiated. See page 853.
Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger
for the ADC. This is a legacy mode which allows code written for previous devices to operate on
this microcontroller.
10.2.2.3
μDMA Trigger Source
Any GPIO pin can be configured to be an external trigger for the μDMA using the GPIO DMA Control
(GPIODMACTL) register. If any GPIO is configured as a non-masked interrupt pin (the appropriate
bit of GPIOIM is set), an interrupt for that port is generated and an external trigger signal is sent to
the μDMA. If the μDMA is configured to start a transfer based on the GPIO signal, a transfer is
initiated.
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July 17, 2013
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