TM4C123GH6PGET Datasheet, PDF (517/1456 Pages) Texas Instruments – Tiva TM4C123GH6PGE Microcontroller

Tiva^™ TM4C123GH6PGE Microcontroller _{(identical to LM4F232H5QD)}
are accessed. In addition, the CLK32EN bit in the HIBCTL register must be set before accessing
any other Hibernation module register.
Note:
The Hibernation module registers are on the Hibernation module clock domain and have
special timing requirements. Software should make use of the WRC bit in the HIBCTL register
to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted
write access is ignored. See “Register Access Timing” on page 507.
Important: The Hibernation module registers are reset under two conditions:
1. Any type of system reset (if the RTCEN and the PINWEN bits in the HIBCTL register
are clear).
2. A cold POR occurs when both the V_DD and V_BAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
Table 7-5. Hibernation Module Register Map
Offset Name
Type
Reset
Description
0x000 HIBRTCC
0x004 HIBRTCM0
0x00C HIBRTCLD
0x010 HIBCTL
0x014 HIBIM
0x018 HIBRIS
0x01C HIBMIS
0x020 HIBIC
0x024 HIBRTCT
0x028 HIBRTCSS
0x030-
0x06F
HIBDATA
RO
R/W
R/W
R/W
R/W
RO
RO
R/W1C
R/W
R/W
R/W
0x0000.0000
0xFFFF.FFFF
0x0000.0000
0x8000.2000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.7FFF
0x0000.0000
-
Hibernation RTC Counter
Hibernation RTC Match 0
Hibernation RTC Load
Hibernation Control
Hibernation Interrupt Mask
Hibernation Raw Interrupt Status
Hibernation Masked Interrupt Status
Hibernation Interrupt Clear
Hibernation RTC Trim
Hibernation RTC Sub Seconds
Hibernation Data
See
page
518
519
520
521
525
527
529
531
532
533
534
7.6 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
July 17, 2013
517
Texas Instruments-Production Data