TMS320C6474_16 Datasheet, PDF (66/215 Pages) Texas Instruments – TMS320C6474 Multicore Digital Signal Processor

TMS320C6474
SPRS552H – OCTOBER 2008 – REVISED APRIL 2011
www.ti.com
HEX ADDRESS
0184 0000
0184 0004 - 0184 001F
0184 0020
0184 0024
0184 0028 - 0184 003F
0184 0040
0184 0044
0184 0048 - 0184 0FFF
0184 1000 - 0184 104F
0184 1050 - 0184 3FFF
0184 4000
0184 4004
0184 4008 - 0184 400C
0184 4010
0184 4014
0184 4018
0184 401C
0184 4020
0184 4024
0184 4030
0184 4034
0184 4038
0184 4040
0184 4044
0184 4048
0184 404C
0184 4050 - 0184 4FFF
0184 5000
0184 5004
0184 5008
0184 500C - 0184 5024
0184 5028
0184 502C - 0184 503C
0184 5040
0184 5044
0184 5048
0184 504C - 0184 5FFF
0184 6000 - 0184 640F
0184 6400 - 0184 7FFF
0184 8000 - 0184 803C
0184 8040
0184 8044
0184 8048
0184 804C - 0184 81FC
0184 8200
0184 8204
0184 8208
Table 5-12. Megamodule Cache Configuration Registers
ACRONYM
L2CFG
-
L1PCFG
L1PCC
-
L1DCFG
L1DCC
-
-
-
L2WBAR
L2WWC
-
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L2WB
L2WBINV
L2INV
-
L1PINV
-
L1DWB
L1DWBINV
L1DINV
-
-
-
-
MAR16
MAR17
MAR18
-
MAR128
MAR129
MAR130
REGISTER NAME
L2 Cache Configuration Register
Reserved
L1P Configuration Register
L1P Cache Control Register
Reserved
L1D Configuration Register
L1D Cache Control Register
Reserved
See Table 5-15, CPU Megamodule Bandwidth Management Registers
Reserved
L2 Writeback Base Address Register - for Block Writebacks
L2 Writeback Word Count Register
Reserved
L2 Writeback and Invalidate Base Address Register - for Block Writebacks
L2 Writeback and Invalidate Word Count Register
L2 Invalidate Base Address Register
L2 Invalidate Word Count Register
L1P Invalidate Base Address Register
L1P Invalidate Word Count Register
L1D Writeback and Invalidate Base Address Register
L1D Writeback and Invalidate Word Count Register
Reserved
L1D Writeback Base Address Register - for Block Writebacks
L1D Writeback Word Count Register
L1D Invalidate Base Address Register
L1D Invalidate Word Count Register
Reserved
L2 Global Writeback Register
L2 Global Writeback and Invalidate Register
L2 Global Invalidate Register
Reserved
L1P Global Invalidate Register
Reserved
L1D Global Writeback Register
L1D Global Writeback and Invalidate Register
L1D Global Invalidate Register
Reserved
See Table 5-13, Megamodule Error Detection Correct Registers
Reserved
Reserved
Controls the Global L2 Locations 1000 0000 - 10FF FFFF
Controls the Global L2 Locations 1100 0000 - 11FF FFFF
Controls the Global L2 Locations 1200 0000 - 12FF FFFF
Reserved
Controls DDR2 CE0 Range 8000 0000 - 80FF FFFF
Controls DDR2 CE0 Range 8100 0000 - 81FF FFFF
Controls DDR2 CE0 Range 8200 0000 - 82FF FFFF
66
C64x+ Megamodule
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