TMS320C6474_16 Datasheet, PDF (120/215 Pages) Texas Instruments – TMS320C6474 Multicore Digital Signal Processor

TMS320C6474
SPRS552H – OCTOBER 2008 – REVISED APRIL 2011
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7.8.3 PLL1 Controller Register Descriptions
This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUG09).
NOTE: The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320C6474 DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUG09) are supported on the C6474 device.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
7.8.3.1 PLL1 Control Register
The PLL control register (PLLCTL) is shown in Figure 7-11 and described in Table 7-25.
31
16
Reserved
R-0
15
8
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7
6
Rsvd
Rsvd
R/W-0 R-1
5
4
Reserved
R/W-0
3
PLLRST
R/W-1
2
Rsvd
R-0
1
PLL
PWRDN
R/W-0
0
PLLEN
R/W-0
Figure 7-11. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100]
Bit Field
31:8 Reserved
7 Reserved
6 Reserved
5:4 Reserved
3 PLLRST
2 Reserved
1 PLLPWRDN
0 PLLEN
Table 7-25. PLL1 Control Register (PLLCTL) Field Descriptions
Value
0
1
0
1
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
PLL reset bit
PLL reset is released
PLL reset is asserted
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL power-down mode select bit
PLL is operational
PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
PLL enable bit
Bypass mode. PLL is bypassed. All the system clocks (SYSCLKn) are divided down directly from
input reference clock.
PLL mode. PLL is not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are
divided down from PLL output.
120 Peripheral Information and Electrical Specifications
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