CC430F5133 Datasheet, PDF (66/121 Pages) Texas Instruments – MSP430™ SoC with RF Core

CC430F613x
CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS554F – MAY 2009 – REVISED DECEMBER 2011
www.ti.com
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference
Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
E_I
Integral linearity error⁽¹⁾
E_D
Differential linearity error⁽¹⁾
E_O
Offset error⁽³⁾
E_G
Gain error⁽³⁾
E_T
Total unadjusted error
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V⁽²⁾
1.6 V < dVREF⁽²⁾
(2)
dVREF ≤ 2.2 V⁽²⁾
dVREF > 2.2 V⁽²⁾
(2)
dVREF ≤ 2.2 V⁽²⁾
dVREF > 2.2 V⁽²⁾
V_CC
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
MIN TYP MAX UNIT
±2.0
LSB
±1.7
±1.0 LSB
±1.0 ±2.0
LSB
±1.0 ±2.0
±1.0 ±2.0 LSB
±1.4 ±3.5
LSB
±1.4 ±3.5
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = V_R+ - V_R-, V_R+ < AVCC, V_R- > AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the CC430 Family User's Guide
(SLAU259).
(3) Parameters are derived using a best fit curve.
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS⁽¹⁾
V_CC
MIN TYP
E_I
Integral linearity ^{ADC12SR = 0, REFOUT = 1}
error ⁽²⁾
ADC12SR = 0, REFOUT = 0
f_ADC12CLK ≤ 4.0 MHz
f_ADC12CLK ≤ 2.7 MHz
2.2 V/3 V
ADC12SR = 0, REFOUT = 1
E_D
Differential
linearity error⁽²⁾
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
f_ADC12CLK ≤ 4.0 MHz
f_ADC12CLK ≤ 2.7 MHz
f_ADC12CLK ≤ 2.7 MHz
-1.0
2.2 V/3 V -1.0
-1.0
E_O
Offset error⁽³⁾
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
f_ADC12CLK ≤ 4.0 MHz
f_ADC12CLK ≤ 2.7 MHz
2.2 V/3 V
±1.0
±1.0
E_G
Gain error⁽³⁾
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
f_ADC12CLK ≤ 4.0 MHz
f_ADC12CLK ≤ 2.7 MHz
2.2 V/3 V
±1.0
E_T
Total unadjusted ^{ADC12SR = 0, REFOUT = 1}
error
ADC12SR = 0, REFOUT = 0
f_ADC12CLK ≤ 4.0 MHz
f_ADC12CLK ≤ 2.7 MHz
2.2 V/3 V
±1.4
MAX UNIT
±1.7
LSB
±2.5
+2.0
+1.5 LSB
+2.5
±2.0
LSB
±2.0
±2.0 LSB
±1.5%⁽⁴⁾ VREF
±3.5 LSB
±1.5%⁽⁴⁾ VREF
(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = V_R+ - V_R-.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.
66
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