CC430F5133 Datasheet, PDF (65/121 Pages) Texas Instruments – MSP430™ SoC with RF Core

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CC430F613x
CC430F612x
CC430F513x
SLAS554F – MAY 2009 – REVISED DECEMBER 2011
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
AV_CC
V_(Ax)
I_{ADC12_A}
PARAMETER
Analog supply voltage
Full performance
Analog input voltage range⁽²⁾
Operating supply current into
AV_CC terminal⁽³⁾
TEST CONDITIONS
AV_CC and DV_CC are connected together,
AV_SS and DV_SS are connected together,
V_(AVSS) = V_(DVSS) = 0 V
All ADC12 analog input pins Ax
f_ADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
V_CC
2.2 V
3V
MIN TYP MAX UNIT
2.2
3.6 V
0
AV_CC V
125 155
µA
150 220
C_I
Input capacitance
Only one terminal Ax can be selected at one
time
2.2 V
20
25 pF
R_I
Input MUX ON resistance
0 V ≤ V_Ax ≤ AV_CC
10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range V_R+ to V_R– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference and REF, Built-In Reference.
(3) The internal reference supply current is not included in current consumption parameter I_{ADC12_A}.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V_CC
MIN TYP
For specified performance of ADC12 linearity
parameters using an external reference voltage or
AVCC as reference.⁽¹⁾
0.45 4.8
f_ADC12CLK ADC conversion clock
For specified performance of ADC12 linearity
parameters using the internal reference.⁽²⁾
2.2 V/3 V
0.45
2.4
For specified performance of ADC12 linearity
parameters using the internal reference.⁽³⁾
0.45 2.4
f_ADC12OSC
Internal ADC12
oscillator ⁽⁴⁾
ADC12DIV = 0, f_ADC12CLK = f_ADC12OSC
2.2 V/3 V
4.2 4.8
t_CONVERT Conversion time
REFON = 0, Internal oscillator,
f_ADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V/3 V
2.4
External f_ADC12CLK from ACLK, MCLK or SMCLK,
(5)
ADC12SSEL ≠ 0
t_Sample
Sampling time
R_S = 400 Ω, R_I = 1000 Ω, C_I = 30 pF,
τ = [R_S + R_I] × C_I ⁽⁶⁾
2.2 V/3 V 1000
MAX UNIT
5.0
4.0 ^MHz
2.7
5.4 MHz
3.1
µs
ns
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with f_ADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) 13 × ADC12DIV × 1/f_ADC12CLK
(6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
t_Sample = ln(2ⁿ⁺¹) x (R_S + R_I) × C_I + 800 ns, where n = ADC resolution = 12, R_S = external source resistance
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