ADS5296A Datasheet, PDF (66/107 Pages) Texas Instruments – 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter

ADS5296A
SBAS631 – OCTOBER 2013
D15
D14
EN_PHASE_
DDR
0
Table 36. Register 42h
D13
D12
D11
D10
0
0
0
0
D7
D6
D5
D4
D3
D2
0
PHASE_DDR1 PHASE_DDR0
0
0
0
All bits default to '0' after reset.
Bit D15
Bits D[14:7]
Bits D[6:5]
Bits D[4:0]
EN_PHASE_DDR
This bit enables LCLK phase programmability.
0 = Disable bits D[6:5] of register 42h
1 = Enable bits D[6:5] of register 42h
Must write '0'
PHASE_DDR[1:0]
These bits control the LCLK output phase relative to data.
Refer to the Programmable LCLK Phase section.
Must write '0'
Table 37. Register 45h
D15
D14
D13
D12
D11
D10
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
All bits default to '0' after reset.
Bits D[15:2]
Bit D1
Bit D0
Must write '0'
PAT_DESKEW_SYNC1
0 = Inactive
1 = Sync pattern mode enabled; ensure that D0 is '0'
PAT_DESKEW_SYNC0
0 = Inactive
1 = Deskew pattern mode enabled; ensure that D1 is '0'
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D9
D8
0
0
D1
D0
0
0
D9
D8
0
0
D1
D0
PAT_DESKEW_SYNC[1:0]
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