TM4C123AE6PM Datasheet, PDF (658/1237 Pages) Texas Instruments – Tiva TM4C123AE6PM Microcontroller

General-Purpose Timers
the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts
is determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count
mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference
between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and
GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode,
the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note
that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater
than the value of GPTMTnPMR and GPTMTnMATCHR. Table 10-8 on page 658 shows the values
that are loaded into the timer registers when the timer is enabled.
Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Register
GPTMTnR
GPTMTnV
GPTMTnPS
GPTMTnPV
Count Down Mode
GPTMTnPR in combination with GPTMTnILR
GPTMTnPR in combination with GPTMTnILR
GPTMTnPR
GPTMTnPR
Count Up Mode
0x0
0x0
0x0
0x0
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements or increments the counter by 1 until
the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM
asserts the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until
it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match
interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the
CnMMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR
and GPTMTnPS registers hold the count of the input events while the GPTMTnV and GPTMTnPV
registers hold the free-running timer value and the free-running prescaler value.In up count mode,
the current count of input events is held in both the GPTMTnR and GPTMTnV registers.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 534.
After the match value is reached in down-count mode, the counter is then reloaded using the value
in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears
the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events
are ignored until TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0
and continues counting.
Figure 10-3 on page 659 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit
after the current count matches the value in the GPTMTnMATCHR register.
658
June 12, 2014
Texas Instruments-Production Data