TM4C123AE6PM Datasheet, PDF (200/1237 Pages) Texas Instruments – Tiva TM4C123AE6PM Microcontroller

JTAG Interface
4.5
4.5.1
4.5.1.1
4.5.1.2
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.
Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3. A
detailed explanation of each instruction, along with its associated Data Register, follows.
Table 4-3. JTAG Instruction Register Commands
IR[3:0]
0x0
0x2
0x8
0xA
0xB
0xE
0xF
All Others
Instruction
EXTEST
SAMPLE / PRELOAD
ABORT
DPACC
APACC
IDCODE
BYPASS
Reserved
Description
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
Shifts data into the ARM Debug Port Abort Register.
Shifts data into and out of the ARM DP Access Register.
Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
Connects TDI to TDO through a single Shift Register chain.
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
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June 12, 2014
Texas Instruments-Production Data