LMK04906_15 Datasheet, PDF (65/113 Pages) Texas Instruments – Ultra Low Noise Clock Jitter Cleaner/Multiplier

LMK04906
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R11[5]
0
1
Table 47. EN_PLL2_XTAL
SNAS589D – JUNE 2012 – REVISED MAY 2013
Oscillator Amplifier State
Disabled
Enabled
REGISTER R12
LD_MUX
LD_MUX sets the output value of the LD pin.
All the outputs logic is active high when LD_TYPE = 3 (Output). All the outputs logic is active low when
LD_TYPE = 4 (Output Inverted). For example, when LD_MUX = 0 (Logic Low) and LD_TYPE = 3 (Output) then
Status_LD outputs a logic low. When LD_MUX = 0 (Logic Low) and LD_TYPE = 4 (Output Inverted) then
Status_LD outputs a logic high.
Table 48. LD_MUX, 5 bits
R12[31:27]
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
Divide
Logic Low
PLL1 DLD
PLL2 DLD
PLL1 & PLL2 DLD
Holdover Status
DAC Locked
Reserved
uWire Readback
DAC Rail
DAC Low
DAC High
PLL1_N
PLL1_N/2
PLL2 N
PLL2 N/2
PLL1_R
PLL1_R/2
PLL2 R ⁽¹⁾
PLL2 R/2 ⁽¹⁾
(1) Only valid when HOLDOVER_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).
LD_TYPE
Sets the IO type of the LD pin.
R12[26:24]
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
Table 49. LD_TYPE, 3 bits
Polarity
Reserved
Reserved
Reserved
Output (push-pull)
Output inverted (push-pull)
Output (open source)
Output (open drain)
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