LMK04906_15 Datasheet, PDF (1/113 Pages) Texas Instruments – Ultra Low Noise Clock Jitter Cleaner/Multiplier

LMK04906
www.ti.com
SNAS589D – JUNE 2012 – REVISED MAY 2013
LMK04906 Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs
Check for Samples: LMK04906
FEATURES
1
•23 Ultra-Low RMS Jitter Performance
– 100 fs RMS Jitter (12 kHz to 20 MHz)
– 123 fs RMS Jitter (100 Hz to 20 MHz)
• Dual Loop PLLatinum™ PLL Architecture
– PLL1
– Integrated Low-Noise Crystal Oscillator
Circuit
– Holdover Mode when Input Clocks are
Lost
– Automatic or Manual
Triggering/Recovery
– PLL2
– Normalized [1 Hz] PLL Noise Floor of -
227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-doubler
– Integrated Low-Noise VCO
• 3 Redundant Input Clocks with LOS
– Automatic and Manual Switch-Over Modes
• 50% Duty Cycle Output Divides, 1 to 1045
(Even and Odd)
• LVPECL, LVDS, or LVCMOS Programmable
Outputs
• Precision Digital Delay, Fixed or Dynamically
Adjustable
• 25 ps Step Analog Delay Control.
• 6 Differential Outputs. Up to 12 Single Ended.
– Up to 5 VCXO/Crystal Buffered Outputs
• Clock Rates of up to 2600 MHz
• 0-Delay Mode
• Three Default Clock Outputs at Power Up
• Multi-mode: Dual PLL, Single PLL, and Clock
Distribution
• Industrial Temperature Range: -40 to 85 °C
• 3.15 V to 3.45 V Operation
• Package: 64-Pin WQFN (9.0 x 9.0 x 0.8 mm)
APPLICATIONS
• 10G/40G/100G OTN Line Cards
• SONET/SDH OC-48/STM-16 and OC-192/STM-
64 Line Cards
• GbE/10GbE, 1/2/4/8/10GFC Line Cards
• ITU G.709 and Custom FEC Line Cards
• Synchronous Ethernet
• Optical Modules
• DSLAM/MSANs
• Test and Measurement
• Broadcast Video
• Wireless Basestations
• Data Converter Clocking
• Microwave ODU and IDUs for Wireless
Backhaul
Backplane
LMK04906
Hitless Switching, Jitter
Cleaning, Frequency
Multiplication, and
Programmable Clock
Distribution
156.25 MHz
LVPECL
100 MHz
LVDS
33.33 MHz
LVCMOS
LMK04906
622.08,
155.52, 77.76,
19.44 MHz
10 GbE
PHY
10 GbE
PHY
FPGA
NPU
SONET
SONET
Figure 1. System Application Diagram
Crystal or
VCXO
OSCout0
Recovered
³GLUW\´ FORFNV
or clean clocks
CLKin0
CLKin1
CLKin2
Backup
Reference
Clock
CLKout0
LMK04906
Precision Clock
Conditioner
CLKout1
CLKout2
CLKout3
CLKout4
LMX2541
PLL+VCO
ADC
FPGA
CPLD
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
Serializer/
Deserializer
DAC
Figure 2. Simplified LMK04906 Block Diagram
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PLLatinum is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated