LMK04906_15 Datasheet, PDF (101/113 Pages) Texas Instruments – Ultra Low Noise Clock Jitter Cleaner/Multiplier

LMK04906
www.ti.com
SNAS589D – JUNE 2012 – REVISED MAY 2013
LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors
close to the LVPECL driver to provide a DC path to ground as shown in Figure 39. For proper receiver operation,
the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical
DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor connected to V_CC and
a 120 Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is
a valid termination as shown in Figure 39 for V_CC = 3.3 V. Note this Thevenin circuit is different from the DC
coupled example in Figure 36.
Vcc
CLKoutX
LVPECL
Driver
CLKoutX*
0.1 PF
0.1 PF
100: Trace
(Differential)
LVPECL
Receiver
Vcc
Figure 39. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent, External Biasing at the
Receiver
Termination for Single-Ended Operation
A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an
unbalanced, single-ended signal.
It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL
driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. When DC coupling one of
the LMK04906 family clock LVPECL drivers, the termination should be 50 Ω to V_CC - 2 V as shown in Figure 40.
The Thevenin equivalent circuit is also a valid termination as shown in Figure 41 for Vcc = 3.3 V.
Vcc - 2V
CLKoutX
LVPECL
Driver
Vcc - 2V
50: Trace
Load
CLKoutX* _50:
Figure 40. Single-Ended LVPECL Operation, DC Coupling
Vcc
CLKoutX
Vcc
LVPECL
Driver
CLKoutX*
50: Trace
Load
Figure 41. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent
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