DP83256_11 Datasheet, PDF (65/146 Pages) Texas Instruments – PLAYER+(TM) Device (FDDI Physical Layer Controller)

5 0 Registers (Continued)
5 20 CURRENT STATE COUNT REGISTER (CSCR)
The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read cycle of this
register
During a Control Bus Interface write cycle the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register
(ICR) will be set to 1 and will ignore a write cycle
ACCESS RULES
ADDRESS
13h
READ
Always
WRITE
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
SCLSCD
CSC6
CSC5
CSC4
CSC3
CSC2
CSC1
CSC0
Bit
Symbol
Description
D0 – D6 CSC0 – CSC6 CURRENT STATE COUNT BIT ^k0 – 6^l Snapshot of the State Counter
Obsolete ^D7
SCLSCD
STATE COUNTER LINE STATE CHANGE DETECTION
64