DP83256_11 Datasheet, PDF (132/146 Pages) Texas Instruments – PLAYER+(TM) Device (FDDI Physical Layer Controller)

8 0 Connection Diagrams (Continued)
TABLE 8-1 DP83256 100-Pin PQFP Pinout Summary (Continued)
Pin No
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Signal Name
Symbol
IO
Pin Type
Control Bus Address^k1^l
CBA1
I
TTL
I O Logic Ground
GND IO
a0V
I O Logic Power
V_CC IO
a5V
Control Bus Address^k2^l
CBA2
I
TTL
Control Bus Address^k3^l
CBA3
I
TTL
Control Bus Address^k4^l
CBA4
I
TTL
Control Bus Address^k5^l
CBA5
I
TTL
Reserved 0
RES 0
a0V
Reserved 1
Control Bus Data^k0^l
Core Ground
Core Power
Control Bus Data^k1^l
Control Bus Data^k2^l
te ^{Control Bus Datak3l}
Control Bus Data^k4^l
Control Bus Data^k5^l
Control Bus Data^k6^l
Control Bus Data^k7^l
le ^{Control Bus Data Parity}
I O Ground
I O Power
Local Symbol Clock
Obso ^{LocalByteClock5}
RES 1
CBD0
IO
GND CORE
V_CC CORE
CBD1
IO
CBD2
IO
CBD3
IO
CBD4
IO
CBD5
IO
CBD6
IO
CBD7
IO
CBP
IO
GND IO
V_CC IO
LSC
O
LBC5
O
a5V
TTL
a0V
a5V
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
a0V
a5V
TTL
TTL
131