DP83256_11 Datasheet, PDF (135/146 Pages) Texas Instruments – PLAYER+(TM) Device (FDDI Physical Layer Controller)

8 0 Connection Diagrams (Continued)
TABLE 8-2 DP83256VF-AP 100-Pin PQFP Pinout Summary (Continued)
Pin No
Signal Name
Symbol
IO
Pin Type
39
Signal Detectb
SDb
I
ECL
40
Signal Detecta
SDa
I
ECL
41
PMD Indicate Datab
PMIDb
I
ECL
42
PMD Indicate Datea
PMIDa
I
ECL
43
Enable Pin 0
EP0
O
TTL
44
Enable Pin 1
EP1
O
TTL
45
ECL Power
46
ECL Ground
V_CC ECL
GND ECL
a5V
a0V
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Receive Clock Inb
RXC INb
I
Receive Clock Ina
RXC INa
I
Receive Data Inb
RXD INb
I
Receive Data Ina
RXD INa
I
Receive Data Outb
RXD OUTb
O
Receive Data Outa
RXD OUTa
O
te ^NoConnect
NC
No Connect
NC
ECL Ground
GND ECL
ECL Power
Reserved 0
V_CC ECL
RES 0
le ^{Reserved 0}
RES 0
PHY Port B Request Data^k0^l
BRD0
I
PHY Port B Request Data^k1^l
BRD1
I
PHY Port B Request Data^k2^l
BRD2
I
PHY Port B Request Data^k3^l
BRD3
I
o _{PHY Port B Request Datak4l}
BRD4
I
I O Ground
GND IO
I O Power
V_CC IO
s _{PHY Port B Request Datak5l}
BRD5
I
PHY Port B Request Data^k6^l
BRD6
I
PHY Port B Request Data^k7^l
BRD7
I
b PHY Port B Request Control
BRC
I
PHY Port B Request Parity
BRP
O
EDevice Reset
ERST
I
Read EWrite
R EW
I
O^{Chip Enable}
ECE
I
ECL
ECL
ECL
ECL
ECL
ECL
a0V
a5V
a0V
a0V
TTL
TTL
TTL
TTL
TTL
a0V
a5V
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
74
EInterrupt
EINT
O
Open Drain
75
EAcknowledge
EACK
O
Open Drain
76
Control Bus Address^k0^l
CBA0
I
TTL
134