DAC34H84_15 Datasheet, PDF (64/96 Pages) Texas Instruments – DAC34H84 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC34H84
SLAS751D – MARCH 2011 – REVISED SEPTEMBER 2015
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Register
Name
config2
Address
0x02
Table 14. Register Name: config2 – Address: 0x02, Default: 0x7000
Bit
Name
15 Reserved
14 dacclkgone_ena
13 dataclkgone_ena
12 collisiongone_ena
11 Reserved
10 Reserved
9 Reserved
8 Reserved
7 sif4_ena
6 mixer_ena
5 mixer_gain
4 nco_ena
3 revbus
2 Reserved
1 twos
0 Reserved
Function
Reserved for factory use.
When set, the DACCLK-gone signal from the clock monitor circuit can
be used to shut off the DAC outputs. The corresponding alarms,
alarm_dacclk_gone and alarm_output_gone, must not be masked (for
example, Config7, bit <10> and bit <8> must set to 0b).
When set, the DATACLK-gone signal from the clock monitor circuit
can be used to shut off the DAC outputs. The corresponding alarms,
alarm_dataclk_gone and alarm_output_gone, must not be masked
(for example, Config7, bit <9> and bit <8> must set to 0b).
When set, the FIFO collision alarms can be used to shut off the DAC
outputs. The corresponding alarms, alarm_fifo_collision and
alarm_output_gone, must not be masked (for example, Config7, bit
<13> and bit <8> must set to 0b).
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
Reserved for factory use.
When set, the serial interface (SIF) is a 4 bit interface, otherwise it is
a 3-bit interface.
When set, the mixer block is enabled.
When set, a 6dB gain is added to the mixer output.
When set, the NCO is enabled. This is not required for coarse mixing.
When set, the input bits for the data bus are reversed. MSB becomes
LSB.
Reserved for factory use.
When set, the input data format is expected to be 2s-complement.
When cleared, the input is expected to be offset-binary.
Reserved for factory use.
Default
Value
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Register
Name
Address
config3 0x03
Table 15. Register Name: config3 – Address: 0x03, Default: 0xF000
Bit
Name
15:12 coarse_dac(3:0)
11:8 Reserved
7:1 Reserved
0 sif_txenable
Function
Scales the output current in 16 equal steps.
I_FS
=
V_EXTIO
R_BIAS
´ 2 ´ (coarse _ dac + 1)
Reserved for factory use.
Reserved for factory use.
When set, the internal value of TXENABLE is set to 1b.
To enable analog output data transmission, set sif_txenable to 1b or
pull CMOS TXENA pin (N9) to high. To disable analog output, set
sif_txenable to 0b and pull CMOS TXENA pin (N9) to low.
Default
Value
1111
0000
0000000
0
Table 16. Register Name: config4 – Address: 0x04, Default: No RESET Value (Write to Clear)
Register
Name
config4
Address
0x04
Bit
Name
15:0 iotest_results(15:0)
Function
Bits in iotest_results with logic value of 1b tell which bit in either DAB[15:0] bus
or DCD[15:0] bus failed during the pattern checker test.
iotest_results(15:8) correspond to the data bits on both DAB[15:8] and
DCD[15:8].
iotest_results(7:0) correspond to the data bits on both DAB[7:0] and DCD[7:0].
Default
Value
No RESET
Value
64
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