DAC34H84_15 Datasheet, PDF (47/96 Pages) Texas Instruments – DAC34H84 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

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DAC34H84
SLAS751D – MARCH 2011 – REVISED SEPTEMBER 2015
PLL alarm
• alarm_from_pll. Occurs when the PLL is out of lock.
Parity alarms
• alarm_Aparity: In dual parity mode, alarm indicating a parity error on the A word. In single parity mode, alarm
on the 32-bit data captured on the rising edge of DATACLKP/N.
• alarm_Bparity: In dual parity mode, alarm indicating a parity error on the B word. In single parity mode, alarm
on the 32-bit data captured on the falling edge of DATACLKP/N.
• alarm_Cparity: In dual parity mode, alarm indicating a parity error on the C word.
• alarm_Dparity: In dual parity mode, alarm indicating a parity error on the D word.
To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_
fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of
TXENA or sif_txenable.
Alarm monitoring is implemented as follows:
• Power up the device using the recommended power-up sequence.
• Clear all the alarms in config5 by setting them to zeros.
• Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.
• Enable automatic DAC shut-off in register config2 if required.
• In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the
DAC outputs will be disabled.
• Read registers config5 to determine which alarm triggered the ALARM pin.
• Correct the error condition and re-synchronize the FIFO.
• Clear the alarms in config5.
• Re-read config5 to ensure the alarm event has been corrected.
• Keep clearing and reading config5 until no error is reported.
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