DAC34H84_15 Datasheet, PDF (24/96 Pages) Texas Instruments – DAC34H84 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC34H84
SLAS751D – MARCH 2011 – REVISED SEPTEMBER 2015
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7.3 Feature Description
7.3.1 Serial Interface
The serial port of the DAC34H84 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC34H84. It is compatible with most synchronous transfer formats and can be configured
as a 3 or 4 pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial interface input
clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in
and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device
with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte
is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Table 1 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes
BIT
Description
R/W
[A6 : A0]
Table 1. Instruction Byte of the Serial Interface
7 (MSB)
6
5
4
3
2
1
0 (LSB)
R/W
A6
A5
A4
A3
A2
A1
A0
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC34H84 and a low indicates a write operation to DAC34H84.
Identifies the address of the register to be accessed during the read or write operation.
Figure 49 shows the serial interface timing diagram for a DAC34H84 write operation. SCLK is the serial interface
clock input to DAC34H84. Serial data enable SDENB is an active low input to DAC34H84. SDIO is serial data in.
Input data to DAC34H84 is clocked on the rising edges of SCLK.
SDENB
SCLK
SDIO
SDENB
Instruction Cycle
Data Transfer Cycle
rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t_S(SDENB)
t_(SCLK)
SCLK
SDIO
t_H(SDIO)
t_S(SDIO)
Figure 49. Serial Interface Write Timing Diagram
T0521-01
Figure 50 shows the serial interface timing diagram for a DAC34H84 read operation. SCLK is the serial interface
clock input to DAC34H84. Serial data enable SDENB is an active low input to DAC34H84. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC34H84 during the data transfer
cycle, while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from the DAC34H84
during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling
edge of SCLK until the rising edge of SDENB when it will 3-state.
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