ADC12D1000_15 Datasheet, PDF (64/86 Pages) Texas Instruments – GSPS Ultra High-Speed ADC

ADC12D1000, ADC12D1600
SNAS480N – MAY 2010 – REVISED AUGUST 2015
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8.1.3.1 Common-Mode and Differential Voltage
The LVDS outputs have selectable common-mode and differential voltage, V_OS and V_OD; see Electrical
Characteristics: Digital Control and Output Pin. See Output Control and Adjust for more information.
Selecting the higher V_OS will also increase V_OD slightly. The differential voltage, V_OD, may be selected for the
higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be realized
with the lower V_OD. This will also result in lower power consumption. If the LVDS lines are long and/or the system
in which the ADC12D1x00 is used is noisy, it may be necessary to select the higher V_OD.
8.1.3.2 Output Data Rate
The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input
clock rate for this device is f_CLK(MIN); see Electrical Characteristics: AC. However, it is possible to operate the
device in 1:2 Demux Mode and capture data from just one 12-bit bus, for example, just DI (or DId) although both
DI and DId are fully operational. This will decimate the data by two and effectively halve the data rate.
8.1.3.3 Terminating Unused LVDS Output Pins
If the ADC is used in Non-Demux Mode, then only the DI and DQ data outputs will have valid data present on
them. The DId and DQd data outputs may be left not connected; if unused, they are internally at TRI-STATE.
Similarly, if the Q-channel is powered-down (that is, PDQ is logic-high), the DQ data output pins, DCLKQ and
ORQ may be left not connected.
8.1.4 Synchronizing Multiple ADC12D1x00s in a System
The ADC12D1x00 has two features to assist the user with synchronizing multiple ADCs in a system; AutoSync
and DCLK Reset. The AutoSync feature is new and designates one ADC12D1x00 as the Master ADC and other
ADC12D1x00s in the system as Slave ADCs. The DCLK Reset feature performs the same function as the
AutoSync feature, but is the first generation solution to synchronizing multiple ADCs in a system; it is disabled by
default. For the application in which there are multiple Master and Slave ADC12D1x00s in a system, AutoSync
may be used to synchronize the Slave ADC12D1x00(s) to each respective Master ADC12D1x00 and the DCLK
Reset may be used to synchronize the Master ADC12D1x00s to each other.
If the AutoSync or DCLK Reset feature is not used, see Table 28 for recommendations about terminating unused
pins.
Table 28. Unused Autosync and DCLK Reset Pin Recommendation
PINS
RCLK+/-
RCOUT1+/-
RCOUT2+/-
DCLK_RST+
DCLK_RST-
UNUSED TERMINATION
Do not connect.
Do not connect.
Do not connect.
Connect to GND through 1-kΩ resistor.
Connect to V_A through 1-kΩ resistor.
8.1.4.1 Autosync Feature
AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1x00s in a system. It
may be used to synchronize the DCLK and data outputs of one or more Slave ADC12D1x00s to one Master
ADC12D1x00. Several advantages of this feature include: no special synchronization pulse required, any upset
in synchronization is recovered upon the next DCLK cycle, and the Master/Slave ADC12D1x00s may be
arranged as a binary tree so that any upset will quickly propagate out of the system.
An example system is shown below in Figure 70 which consists of one Master ADC and two Slave ADCs. For
simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one
another.
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