TPS65916_17 Datasheet, PDF (63/89 Pages) Texas Instruments – 3.1-V to 5.2-V, 5 Buck Converter and 5 LDO Power Management IC (PMIC)

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TPS65916
SLVSD09B – MARCH 2016 – REVISED MARCH 2017
• Burst access (read or write)
– This mode consists of fetching and storing several data at contiguous locations. The protocol is
shown in Figure 5-22.
– The R/W bit is always provided first, followed by page address and register address fields. When
the R/W bit 0, a read access is performed. When the R/W bit 1, a write access is performed.
– One burst bit indicates if the following transfer is a single access (BURST = 0) or a burst access
(BURST = 1).
– Four unused bits follow the burst bit and packets of 8-bit data are finally either shifted in (write) or
out (read).
– The transaction remains active as long as the SCE signal is maintained high by the host.
– The address is automatically incremented internally for each new 8-bit packet received.
– The host must pull the SCE signal low after a complete 8-bit data is transferred, otherwise the last
transaction is discarded.
– For a write access, the data output line SDO is invalid (useless) during the whole transaction.
– For a read access, the data output line SDO is invalid during the unused bits (time slot used for
data fetch) and then becomes active or valid after the unused bits.
5.12.2.2 SPI Protocol
Figure 5-21 shows the SPI protocol for a single read and write access. Figure 5-22 shows the SPI protocol
for a burst read and write access.
SPI write
SCE
SCK
SDI
(SDI)
RW Page
Register address (8)
Burst Unused bits (5)
Data (8)
Palmas samples SDI on SCK rising edge
: 0DVWHU WR DVVHUW GDWD RQ IDOOLQJ HGJH
SPI read
SCE
SCK
SDI
(SDI)
RW Page
Register address (8)
Burst Unused bits (5)
'RQ¶W &DUH
SDO
(SDO)
Data (8)
Palmas samples SDI on SCK rising edge
: 0DVWHU WR DVVHUW GDWD RQ IDOOLQJ HGJH
PMIC asserts SDO so that it is available on SCK rising edge
: Master must sample data on rising edge
Figure 5-21. SPI Single Read and Write Access
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