TPS65916_17 Datasheet, PDF (61/89 Pages) Texas Instruments – 3.1-V to 5.2-V, 5 Buck Converter and 5 LDO Power Management IC (PMIC)

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TPS65916
SLVSD09B – MARCH 2016 – REVISED MARCH 2017
The master then generates a REPEATED START condition (a REPEATED START condition has the
same timing as the START condition). After the REPEATED START condition, the protocol is the same as
F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS
mode and switches all the internal settings of the slave devices to support F/S mode. Instead of using a
STOP condition, REPEATED START conditions are used to secure the bus in HS mode.
Attempting to read data from register addresses not listed in this section results in a read out of 0xFF.
DATA
CLK
S
START
condition
Figure 5-17. START and STOP Conditions
P
STOP
condition
DATA
CLK
Data line stable;
data valid
Change of data allowed
Figure 5-18. Bit Transfer on the Serial Interface
Data output
by transmitter
Data output
by receiver
SCL from
master
S
START
condition
Not Acknowledge
Acknowledge
1
2
8
Figure 5-19. Acknowledge on the I²C Bus
9
Clock pulse for
acknowledgement
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Detailed Description
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