F28M36P63C_14 Datasheet, PDF (63/254 Pages) Texas Instruments – F28M36x Concerto™ Microcontrollers

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F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.13 Analog Subsystem Clocking
The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as
defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the
C28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog
Subsystem resets—ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of
ASYSCLK, it is possible for the Cortex-M3 software to restore the ASYSCLK to its default value by
resetting the Analog Subsystem.
The ASYSCLK is shut down when the Cortex-M3 processor enters the Deep Sleep mode.
3.14 Shared Resources Clocking
The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK.
The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register.
In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL
register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore,
EPI is clocked by M3SSCLK.
3.15 Loss of Input Clock (NMI Watchdog Function)
The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of
the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external
crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the
XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main
clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to
enable other chip components to take corrective or recovery action from such event (see Figure 3-13).
The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator)
so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing
source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex-M3 NMI
circuit, the C28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses
an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK.
Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control
outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a
corresponding CPU, while starting the associated NMI watchdog counter.
If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in
the device reset. If the software does react to the NMI, the software can prevent the impending reset by
disabling the watchdog timers, and then the software can initiate necessary corrective action such as
switching over to an alternative clock source (if available) or the software can initiate a shut-down
procedure for the system.
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