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F28M36P63C_14 Datasheet, PDF (1/254 Pages) Texas Instruments – F28M36x Concerto™ Microcontrollers | |||
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F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C â OCTOBER 2012 â REVISED FEBRUARY 2014
F28M36x Concerto⢠Microcontrollers
1 Device Summary
1.1 Features
1
⢠Master Subsystem â ARM® Cortex®-M3
â 125 MHz
â Cortex-M3 Core Hardware Built-in Self-Test
â Embedded Memory
⢠Up to 1MB of Flash (ECC)
⢠Up to 128KB of RAM (ECC or Parity)
⢠Up to 64KB of Shared RAM
⢠2KB of IPC Message RAM
â 5 Universal Asynchronous
Receiver/Transmitters (UARTs)
â 4 Synchronous Serial Interfaces (SSIs)
and Serial Peripheral Interface (SPI)
â 2 Inter-integrated Circuits (I2Cs)
â Universal Serial Bus On-the-Go (USB-OTG) +
PHY
â 10/100 ENET 1588 MII
â 2 Controller Area Networks (CANs)
â 32-Channel Micro Direct Memory Access
(µDMA)
â Dual Security Zones (128-Bit Password per
Zone)
â External Peripheral Interface (EPI)
â Micro Cyclic Redundancy Check (µCRC)
Module
â 4 General-Purpose Timers
â 2 Watchdog Timer Modules
â Endianness: Little Endian
⢠Clocking
â On-chip Crystal Oscillator and External Clock
Input
â Dynamic Phase-Locked Loop (PLL) Ratio
Changes Supported
⢠1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design
⢠Interprocessor Communications (IPC)
â 32 Handshaking Channels
â 4 Channels Generate IPC Interrupts
â Can be Used to Coordinate Transfer of Data
Through IPC Message RAMs
⢠Up to 142 Individually Programmable, Multiplexed
General-Purpose Input/Output (GPIO) Pins
â Glitch-free I/Os
⢠Control Subsystem â TMS320C28x 32-Bit CPU
â 150 MHz
â C28x Core Hardware Built-in Self-Test
â Embedded Memory
⢠Up to 512KB of Flash (ECC)
⢠Up to 36KB of RAM (ECC or Parity)
⢠Up to 64KB of Shared RAM
⢠2KB of IPC Message RAM
â IEEE-754 Single-Precision Floating-Point Unit
(FPU)
â Viterbi, Complex Math, CRC Unit (VCU)
â Serial Communications Interface (SCI)
â SPI
â I2C
â 6-Channel Direct Memory Access (DMA)
â 12 Enhanced Pulse Width Modulator (ePWM)
Modules
⢠24 Outputs (16 High-Resolution)
â 6 32-Bit Enhanced Capture (eCAP) Modules
â 3 32-Bit Enhanced Quadrature Encoder Pulse
(eQEP) Modules
â Multichannel Buffered Serial Port (McBSP)
â EPI
â One Security Zone (128-Bit Password)
â 3 32-Bit Timers
â Endianness: Little Endian
⢠Analog Subsystem
â Dual 12-Bit Analog-to-Digital Converters (ADCs)
â Up to 2.88 MSPS
â Up to 24 Channels
â 4 Sample-and-Hold (S/H) Circuits
â Up to 6 Comparators With 10-Bit Digital-to-
Analog Converter (DAC)
⢠Package
â 289-Ball ZWT New Fine Pitch Ball Grid Array
(nFBGA)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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