F28M36P63C_14 Datasheet, PDF (40/254 Pages) Texas Instruments – F28M36x Concerto™ Microcontrollers

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
www.ti.com
Table 3-18. Master Subsystem Boot Mode Selection
Boot Mode #
0⁽²⁾
1⁽²⁾
Master Subsystem Boot Modes
Boot from Parallel GPIO
Boot to Master Subsystem RAM
PF2_GPIO34
(BOOT_3)⁽¹⁾
0
0
PF3_GPIO35
(BOOT_2)⁽¹⁾
0
0
PG7_GPIO47
(BOOT_1)⁽¹⁾
0
0
PG3_GPIO43
(BOOT_0)⁽¹⁾
0
1
2⁽²⁾
Boot from Master Subsystem serial peripherals
(UART0/SSI0/I2C0)
0
0
1
0
3⁽²⁾
Boot from Master Subsystem CAN interface
0
0
1
1
4⁽²⁾
Boot from Master Subsystem Ethernet interface
0
1
0
0
5⁽²⁾⁽⁴⁾
Not supported (Defaults to Boot-to-Flash),
future boot from Cortex-M3 USB
0
1
0
1
6^(2)(4)(5)
Boot-to-OTP
0
1
1
0
7⁽²⁾⁽⁴⁾
Boot to Master Subsystem Flash memory
0
1
1
1
8
Not supported (Defaults to Boot-to-Flash)
1
0
0
0
9⁽⁴⁾
Boot from Master Subsystem serial peripheral –
SSI0 Master
1
0
0
1
10⁽⁴⁾
Boot from Master Subsystem serial peripheral –
I2C0 Master
1
0
1
0
11⁽⁴⁾
Not supported (Defaults to Boot-to-Flash)
1
0
1
1
12⁽³⁾
Boot from Master Subsystem Ethernet interface
1
1
0
0
13⁽⁴⁾
Not supported (Defaults to Boot-to-Flash)
1
1
0
1
14⁽⁴⁾
Not supported (Defaults to Boot-to-Flash)
1
1
1
0
15⁽⁴⁾
Boot to Master Subsystem Flash memory
1
1
1
1
(1) By default, GPIO terminals are not pulled up (they are floating).
(2) Boot Modes 0–7 are pin-compatible with the F28M35x members of the Concerto family (they use same GPIO terminals).
(3) Boot Mode 12 is the same as Boot Mode 4, except it uses a different set of GPIO terminals.
(4) This Boot Mode uses a faster Flash power-up sequence. The maximum supported OSCCLK frequency for this mode is 30 MHz.
(5) Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash.
Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the
Master Flash memory. This branching requires that the Master Flash be already programmed with valid
code; otherwise, a hard fault exception is generated and the Cortex-M3 goes back to the above reset
sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until
the emulator is connected and a debug session started.) If the Master Subsystem Flash has already been
programmed, the application code will start execution. Typically, the Master Subsystem application code
will then establish data communication with the C28x [through the IPC (Interprocessor Communications
peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Boot Mode 15 (Fast
Boot to Flash Mode) supported on this device is a special boot to Flash mode, which configures Flash for
a faster power up, thus saving some boot time. Boot Mode 7 and other modes which default to Flash do
not configure Flash for a faster power up like Boot Mode 15 does. Note that following reset, the internal
pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically require four
external pullups.
Boot Mode 1 causes the Master boot program to branch to Cortex-M3 RAM, where the Cortex-M3
processor starts executing code that has been preloaded earlier. Typically, this mode is used during
development of application code meant for Flash, but which has to be first tested running out of RAM. In
this case, the user would typically load the application code into RAM using the debugger, and then issue
a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot
process on the Master Subsystem side is controlled by the application code.
Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external
peripheral before branching to the application code. This process is different from the process in Boot
Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into
RAM by the emulator. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of
M-Boot ROM) will start uploading the Master application code from preselected Parallel GPIO_MUX pins.
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