DAC39J82_16 Datasheet, PDF (62/147 Pages) Texas Instruments – Digital-to-Analog Converter

DAC39J82
SLASE47 – JANUARY 2015
www.ti.com
Name
config32
config33
config34
config35
config36
config37
config38
config39
config40
config41
config42
config43
config44
config45
config46
config47
config48
config49
config50
config51
config52
config53
config54
config55
config56
config57
config58
config59
config60
config61
config62
config63
config64
config65
config66
Address
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
Default
0x0000
0x0000
0x1B1B
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0xFFFF
0x0004
0x0000
0x0000
0x0000
0x0100
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Table 29. Register Map (continued)
(MSB)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
syncsel_dither(3:0)
reserved
syncsel_pap(3:0)
syncsel_fir5a(3:0)
reserved
patha_in_sel(1:0)
pathb_in_sel(1:0)
reserved
reserved
patha_out_sel(1:0)
pathb_out_sel(1:0)
pathc_out_sel(1:0)
pathd_out_sel(1:0)
sleep_cntl(15:0)
reserved
cdrvser_sysref_mode(2:0)
reserved
reserved
clkjesd_div(2:0)
reserved
reserved
reserved
reserved
reserved
dither_ena(3:0)
dither_mixer_ena(3:0)
dither_sra_sel3:0)
reserved
reserved dither _zero
reserved(15:0)
reserved(15:0)
reserved(15:0)
reserved(15:0)
reserved(15:0)
reserved(15:0)
reserved
reserved
pap_
dlylen_sel
pap_gain(2:0)
pap_vth(15:0)
reserved
titest_dieid
_read_ena
reserved
reserved
reserved reserved sifdac_ena
sifdac(15:0)
lockdet_adj(2:0)
pll_reset
pll_ndivsync
_ena
pll_ena
pll_cp(1:0)
pll_n(4:0)
memin_pll_lfvolt(2:0)
pll_m(7:0)
pll_p(3:0)
reserved
pll_vcosel
pll_vco(5:0)
pll_vcoitune(1:0)
pll_cp_adj(4:0)
reserved
syncb
_lvds
_lopwrb
syncb
_lvds
_lopwra
syncb _lvds
_lpsel
syncb
_lvds
_effuse
_sel
reserved
reserved
lvds
_sleep
lvds
_sub_ena
reserved(6:0)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
serdes
_clk_sel
serdes_refclk_div(3:0)
reserved
reserved
rw_cfgpll(15:0)
reserved
rw_cfgrx0(14:0)
rw_cfgrx0(15:0)
reserved
INVPAIR(7:0)
reserved
errorcnt_link0(15:0)
errorcnt_link1(15:0)
62
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