DAC39J82_16 Datasheet, PDF (30/147 Pages) Texas Instruments – Digital-to-Analog Converter

DAC39J82
SLASE47 – JANUARY 2015
Table 3. Relationship Between Lane Rate and SerDes PLL Output
Frequency (continued)
RATE
Quarter
Eigth
LINE RATE
x Gbps
x Gbps
PLL OUTPUT FREQUENCY
1x GHz
2x GHz
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Table 4. SerDes PLL Modes Selection
MPY
00010000
00010100
00011000
00100000
00100001
00101000
00110000
00110010
00111100
01000000
01000010
01010000
01011000
01100100
Other codes
EFFECT
4x
5x
6x
8x
8.25x
10x
12x
12.5x
15x
16x
16.5x
20x
22x
25x
reserved
The wide range of multiply factors combined with the different rate modes means it will often be possible to
achieve a given line rate from multiple different reference frequencies. The configuration which utilizes the
highest reference frequency achievable is always preferable.
The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop
filter depending on the operating frequency of the VCO. To indicate the selection the user must set the rw_cfgpll
[9] (VRANGE) bit. If the PLL output frequency is below 2.17 GHz, VRANGE should be set high.
Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock
by setting the appropriate loop bandwidth via rw_cfgpll [12:11] (LB) bits. The loop bandwidth is obtained by
dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and PLL output
frequency as shown in Table 5.
Table 5. SerDes PLL Loop Bandwidth Selection
LB
EFFECT
00 Medium loop bandwidth
01 Ultra high loop bandwidth
10 Low loop bandwidth
11 High loop bandwidth
BWSCALE vs PLL OUTPUT FREQUENCY
3.125 GHz
2.17 GHz
1.5625 GHz
13
14
16
7
8
8
21
23
30
10
11
14
An approximate loop bandwidth of 8–30 MHz is suitable and recommended for most systems where the
reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input
cell, but of low quality, an approximate loop bandwidth of less than 8 MHz may offer better performance. For
systems where the reference clock is cleaned via an ultra low jitter LC-based cleaner PLL, a high loop bandwidth
up to 60MHz is more appropriate. Note that the use of ultra high loop bandwidth setting is not recommended for
PLL multiply factor of less than 8.
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