ADC3421 Datasheet, PDF (62/79 Pages) Texas Instruments – Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter

ADC3421, ADC3422, ADC3423, ADC3424
SBAS673A – JULY 2014 – REVISED OCTOBER 2015
9.6.1.23 Register 239h (address = 239h)
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Figure 169. Register 239h
7
6
5
4
0
0
0
0
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
SP1 CHD
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
Table 32. Register 239h Field Descriptions
Bit Field
7-4 0
3
SP1 CHD
2-0 0
Type
W
R/W
Reset
0h
0h
W
0h
Description
Must write 0.
This bit sets the special mode for best performance on channel
D.
Always write 1 after reset.
Must write 0.
9.6.1.24 Register 308h (address = 308h)
Figure 170. Register 308h
7
6
5
4
3
HIGH IF MODE<5:4>
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
2
0
W-0h
1
0
R/W-0h
0
0
W-0h
Bit Field
7-6 HIGH IF MODE<5:4>
5-0 0
Table 33. Register 308h Field Descriptions
Type
R/W
W
Reset
0h
0h
Description
Set the HIGH IF MODE[7:0] bits together to FFh.
Improves HD3 by a couple of dB for IF > 100 MHz.
Must write 0.
9.6.1.25 Register 41Dh (address = 41Dh)
Figure 171. Register 41Dh
7
6
5
4
3
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
2
0
W-0h
1
HIGH IF MODE2
R/W-0h
0
0
W-0h
Bit Field
7-2 0
1
HIGH IF MODE2
0
0
Table 34. Register 41Dh Field Descriptions
Type
W
R/W
W
Reset
0h
0h
0h
Description
Must write 0.
Set the HIGH IF MODE[7:0] bits together to FFh.
Improves HD3 by a couple of dB for IF > 100 MHz.
Must write 0.
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