ADC3421 Datasheet, PDF (44/79 Pages) Texas Instruments – Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter

ADC3421, ADC3422, ADC3423, ADC3424
SBAS673A – JULY 2014 – REVISED OCTOBER 2015
www.ti.com
The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs for the device) which is set by
the noise of the clock input buffer and the external clock. T_Jitter can be calculated with Equation 3.
T_Jitter
(T ) (T ) 2
Jitter ,Ext.Clock _ Input
2
Aperture_ ADC
(3)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input; a faster clock slew rate improves the ADC aperture jitter. The devices have a typical
thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external
jitter for different input frequencies, is shown in Figure 137.
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
66.5
66.0
65.5
65.0
10
Ext Clock Jitter
35 fs
50 fs
100 fs
150 fs
200 fs
100
Input Frequency (MHz)
1000
D03061
Figure 137. SNR vs Frequency for Different Clock Jitter
9.3.3 Digital Output Interface
The devices offer two different output format options, thus making interfacing to a field-programmable gate array
(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using
the serial interface, as shown in Table 3. The output interface options are:
• One-wire, 1x frame clock, 12x serialization with the DDR bit clock and
• Two-wire, 1x frame clock, 6x serialization with the DDR bit clock.
Table 3. Interface Rates
INTERFACE
OPTIONS
One-wire
Two-wire
(Default after
Reset)
SERIALIZATION
12x
6x
RECOMMENDED SAMPLING
FREQUENCY (MSPS)
MINIMUM
MAXIMUM
15
80
20 ⁽¹⁾
125
BIT CLOCK
FREQUENCY
(MHz)
90
480
60
375
(1) Use the LOW SPEED ENABLE register bits for low speed operation; see Table 21.
FRAME CLOCK
FREQUENCY
(MHz)
15
80
20
125
SERIAL DATA
RATE PER
WIRE (Mbps)
180
960
120
750
9.3.3.1 One-Wire Interface: 12x Serialization
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The
data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at
the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x
serialization).
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