ADS54J69 Datasheet, PDF (61/75 Pages) Texas Instruments – Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter

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STEP
SEQUENCE
Set the value of K and the
5
SYSREF signal frequency
accordingly
6
JESD lane alignment
ADS54J69
SBAS713B – MAY 2015 – REVISED FEBRUARY 2016
Table 58. Initialization Sequence (continued)
DESCRIPTION
Write address 4-003h with 00h and address 4-004h with 69h.
Write address 6-006h with XXh (choose the value of K).
Pull the SYNC pin (pin 63) low.
Pull the SYNC pin high.
PAGE BEING
PROGRAMMED
COMMENT
—
Select the JESD digital page.
JESD
digital page
(JESD bank)
Default value of K is 8 for 20X (4-lane) mode and 4 for 40X (2-lane) mode.
However, K can be programmed for higher values than the default by using
bits 4-0 of address 6-006 in the JESD digital page. For example, if K = 31 by
writing address 6-006h with 1Fh in the JESD digital page, then the SYSREF
signal frequency must be kept less than or equal to 250 MHz / 32 =
7.8125 MHz.
Transmit K28.5 characters.
—
After the receiver is synchronized, initiate an ILA phase and subsequent
transmissions of ADC data.
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