ADS54J69 Datasheet, PDF (24/75 Pages) Texas Instruments – Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter

ADS54J69
SBAS713B – MAY 2015 – REVISED FEBRUARY 2016
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Feature Description (continued)
The input bandwidth shown in Figure 60 is measured with respect to a 50-Ω differential input termination at the
ADC input pins.
0
-3
-6
-9
-12
-15
-18
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Input Frequency (MHz)
D057
Figure 60. Transfer Function versus Frequency
7.3.2 DDC Block
The ADS54J69 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is
followed by a DDC block consisting of a decimate-by-2, half-band, finite impulse response (FIR) filter with low-
pass and high-pass options programmable via the SPI interface.
7.3.2.1 Decimate-by-2 Filter
This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness
is ±0.05 dB. Table 1 shows corner frequencies for the low-pass and high-pass filter options.
Table 1. Corner Frequencies for the Decimate-by-2 Filter
CORNERS (dB)
–0.1
–0.5
–1
–3
LOW PASS
0.202 × f_S
0.210 × f_S
0.215 × f_S
0.227 × f_S
HIGH PASS
0.298 × f_S
0.290 × f_S
0.285 × f_S
0.273 × f_S
Figure 61 and Figure 62 show the frequency response of the decimate-by-2 filter from dc to f_S / 2.
5
-20
-45
-70
-95
-120
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency Response
D013
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
0
0.05
0.1
0.15
0.2
Frequency Response
0.25
D014
Figure 61. Decimate-by-2 Filter Response
Figure 62. Decimate-by-2 Filter Response (Zoomed)
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